In recent years, ReRAM (Resistive RAM) in which a variable resistance element that reversibly changes its resistance value is utilized as memory, has been proposed. Moreover, in this ReRAM, a structure where the variable resistance element is provided between a word line extending parallel to a substrate and a bit line extending perpendicularly to the substrate, is known. This structure enables an even higher degree of integration of a memory cell array to be achieved. In a memory cell array of such a structure, a plurality of the bit lines are connected to one global bit line, via select transistors.
However, in the memory cell array of such a structure, as the number of times of executions of a write operation/erase operation to a memory cell increases, the select transistor gradually deteriorates. So a memory cell in a periphery of the select transistor may cause a write defect. Therefore, it is important to detect deterioration of such a select transistor.